The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Mar. 27, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Christopher J. Hughes, Santa Clara, CA (US);

Jonathan D. Pearce, Hillsboro, OR (US);

Guei-Yuan Lueh, San Jose, CA (US);

ElMoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Jorge E. Parra, El Dorado Hills, CA (US);

Prasoonkumar Surti, Folsom, CA (US);

Krishna N. Vinod, San Jose, CA (US);

Ronen Zohar, Sunnyvale, CA (US);

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Int. Cl.
CPC ...
G06F 9/30 (2018.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 9/30018 (2013.01); G06F 9/30021 (2013.01); G06F 9/30036 (2013.01); G06F 9/3887 (2013.01);
Abstract

Embodiments detailed herein relate to reduction operations on a plurality of data element values. In one embodiment, a process comprises decoding circuitry to decode an instruction and execution circuitry to execute the decoded instruction. The instruction specifies a first input register containing a plurality of data element values, a first index register containing a plurality of indices, and an output register, where each index of the plurality of indices maps to one unique data element position of the first input register. The execution includes to identify data element values that are associated with one another based on the indices, perform one or more reduction operations on the associated data element values based on the identification, and store results of the one or more reduction operations in the output register.


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