The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 05, 2022

Filed:

Dec. 23, 2020
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Igor Arsovski, Williston, VT (US);

John R. Goss, South Burlington, VT (US);

Eric D. Hunt-Schroeder, South Burlington, VT (US);

Andrew K. Killorin, Weybridge, VT (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01);
Abstract

Systems and methods are provided for implementing customer-transparent logic redundancy in scan chains for improved yield of integrated circuits. More specifically, an integrated circuit structure is provided for that includes a plurality of combined latch structures. Each of the combined latch structures includes an original latch and a redundant latch. The integrated circuit structure further includes a plurality of combined logic structures. Each of the combined logic structures includes an original logic structure a redundant logic structure. Each redundant latch is a duplicate of each respective original latch within a combined latch structure and each redundant logic structure is a duplicate of each respective original logic structure within a combined logic structure such that a two-fold library of latches and logic is provided for one or more scan chains of the integrated circuit structure.


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