The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2022
Filed:
Sep. 23, 2020
Qualcomm Incorporated, San Diego, CA (US);
Foua Vang, Sacramento, CA (US);
Hyeokjin Lim, San Diego, CA (US);
Seung Hyuk Kang, San Diego, CA (US);
Venugopal Boynapalli, San Diego, CA (US);
Shitiz Arora, San Diego, CA (US);
QUALCOMM INCORPORATED, San Diego, CA (US);
Abstract
A MOS IC includes a MOS logic cell that includes first and second sets of transistor logic in first and second subcells, respectively. The first and second sets of transistor logic are functionally isolated from each other. The MOS logic cell includes a first set of Mlayer interconnects on an Mlayer extending in a first direction over the first and second subcells. A first subset of the first set of Mlayer interconnects is coupled to inputs/outputs of the first set of transistor logic in the first subcell and is unconnected to the second set of transistor logic. Each of the first subset of the first set of Mlayer interconnects extends from the corresponding input/output of the first set of transistor logic of the first subcell to the second subcell, and is the corresponding input/output of the first set of transistor logic.