The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Dec. 10, 2019
Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Hao-Chieh Chan, Hsinchu, TW;

Chung-Hui Chen, Hsinchu, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 49/02 (2006.01); H01L 23/522 (2006.01); H01L 21/8234 (2006.01); H01L 27/088 (2006.01); H01L 21/762 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/08 (2006.01); H01L 27/06 (2006.01); H01L 29/94 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 28/60 (2013.01); H01L 21/76224 (2013.01); H01L 21/823431 (2013.01); H01L 23/5223 (2013.01); H01L 27/0629 (2013.01); H01L 27/0805 (2013.01); H01L 27/0886 (2013.01); H01L 28/90 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01); H01L 29/94 (2013.01); H01L 27/0207 (2013.01); H01L 27/0808 (2013.01);
Abstract

A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.


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