The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

Nov. 14, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventor:

Frederick Chen, Tainan, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 45/00 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/417 (2006.01); H01L 29/78 (2006.01); H01L 21/265 (2006.01); H01L 21/306 (2006.01); H01L 21/74 (2006.01); H01L 29/66 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2436 (2013.01); H01L 21/26513 (2013.01); H01L 21/30604 (2013.01); H01L 21/74 (2013.01); H01L 27/2463 (2013.01); H01L 29/0847 (2013.01); H01L 29/1083 (2013.01); H01L 29/41791 (2013.01); H01L 29/66492 (2013.01); H01L 29/66515 (2013.01); H01L 29/66795 (2013.01); H01L 29/7833 (2013.01); H01L 29/7851 (2013.01); H01L 45/08 (2013.01); H01L 45/16 (2013.01);
Abstract

A resistive random access memory (RRAM) device is provided. The RRAM device includes a gate structure on a substrate, and a source region and a drain region disposed on opposite sides of the gate structure on the substrate. The source region includes a semiconductor bulk, and the drain region includes a plurality of semiconductor fins adjacent to the semiconductor bulk, wherein the semiconductor fins are separated from each other by an isolation layer. The RRAM device further includes a plurality of RRAM units, wherein each of the RRAM units electrically contacts one of the semiconductor fins.


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