The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 29, 2022

Filed:

May. 12, 2020
Applicant:

Renesas Electronics Corporation, Tokyo, JP;

Inventors:

Shigeo Tokumitsu, Tokyo, JP;

Yoshiki Maruyama, Tokyo, JP;

Satoshi Iida, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/74 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 29/66 (2006.01); H01L 21/306 (2006.01);
U.S. Cl.
CPC ...
H01L 21/743 (2013.01); H01L 21/30604 (2013.01); H01L 23/481 (2013.01); H01L 23/528 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes: providing a substrate, forming a first opening, forming a first insulating layer, forming a second opening, embedding a conductive layer, forming a protective layer, and performing CMP. The substrate includes a semiconductor substrate and a semiconducting layer. The conductive layer is embedded in the second opening so that a gap along a thickness direction of the semiconducting layer is formed. The protective layer is formed in the second opening on at least a portion of a surfaces of the conductive layer. In the CMP step, a portion of the conductive layers formed outside the second opening is removed.


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