The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 29, 2022
Filed:
Mar. 26, 2020
Western Digital Technologies, Inc., San Jose, CA (US);
Tomer Tzvi Eliash, Sunnyvale, CA (US);
Alexander Bazarsky, Holon, IL;
WESTERN DIGITAL TECHNOLOGIES, INC., San Jose, CA (US);
Abstract
Methods and apparatus for use with non-volatile memory (NVM) arrays having single-level cell (SLC) layers and multi-level cell (MLC) layers, such as triple-level cell (TLC) layers, provide for a coupled SLC/MLC write operation where SLC write protection is combined into a MLC write flow. In an illustrative example, data is written concurrently to SLC and TLC. The SLC data provides a backup for the TLC data in the event the TLC data is defective. The TLC data is verified using, for example, write verification. If the data is successfully verified, the SLC block can be erased or otherwise overwritten with new data. If not, the SLC block can be used to recover the data for storage in a different TLC block. The coupled SLC/MLC write operation may be performed in conjunction with a quick pass write (QPW).