The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Dec. 20, 2019
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Ned M. Smith, Beaverton, OR (US);

Kshitij Arun Doshi, Tempe, AZ (US);

Francesc Guim Bernat, Barcelona, ES;

Mona Vij, Hillsboro, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 9/32 (2006.01); H04L 9/08 (2006.01); G06F 21/78 (2013.01); H04L 29/06 (2006.01); G06F 12/14 (2006.01); G06F 9/455 (2018.01); G06F 16/18 (2019.01); G06F 16/23 (2019.01); G06F 11/10 (2006.01); H04L 9/06 (2006.01); H04L 41/0893 (2022.01); H04L 41/5009 (2022.01); H04L 41/5025 (2022.01); H04L 43/08 (2022.01); H04L 67/1008 (2022.01); G06F 9/54 (2006.01); G06F 21/60 (2013.01); H04L 9/00 (2022.01); H04L 41/0896 (2022.01); H04L 41/142 (2022.01); H04L 41/5051 (2022.01); H04L 67/141 (2022.01); H04L 41/14 (2022.01); H04L 47/70 (2022.01); H04L 67/12 (2022.01); G06F 8/41 (2018.01); G06F 9/38 (2018.01); G06F 9/445 (2018.01); G06F 9/48 (2006.01); G06F 9/50 (2006.01); G06F 11/34 (2006.01); G06F 21/62 (2013.01); H04L 67/10 (2022.01); G16Y 40/10 (2020.01);
U.S. Cl.
CPC ...
H04L 9/3297 (2013.01); G06F 8/443 (2013.01); G06F 9/3836 (2013.01); G06F 9/44594 (2013.01); G06F 9/45533 (2013.01); G06F 9/4881 (2013.01); G06F 9/505 (2013.01); G06F 9/544 (2013.01); G06F 11/1004 (2013.01); G06F 11/3433 (2013.01); G06F 12/1408 (2013.01); G06F 16/1865 (2019.01); G06F 16/2322 (2019.01); G06F 21/602 (2013.01); H04L 9/008 (2013.01); H04L 9/0637 (2013.01); H04L 9/0822 (2013.01); H04L 9/0825 (2013.01); H04L 9/0866 (2013.01); H04L 41/0893 (2013.01); H04L 41/0896 (2013.01); H04L 41/142 (2013.01); H04L 41/145 (2013.01); H04L 41/5009 (2013.01); H04L 41/5025 (2013.01); H04L 41/5051 (2013.01); H04L 43/08 (2013.01); H04L 47/822 (2013.01); H04L 63/0407 (2013.01); H04L 63/0428 (2013.01); H04L 63/1408 (2013.01); H04L 63/20 (2013.01); H04L 67/1008 (2013.01); H04L 67/12 (2013.01); H04L 67/141 (2013.01); G06F 2209/509 (2013.01); G16Y 40/10 (2020.01); H04L 67/10 (2013.01); H04L 2209/127 (2013.01);
Abstract

Various approaches for memory encryption management within an edge computing system are described. In an edge computing system deployment, a computing device includes capabilities to store and manage encrypted data in memory, through processing circuitry configured to: allocate memory encryption keys according to a data isolation policy for a microservice domain, with respective keys used for encryption of respective sets of data within the memory (e.g., among different tenants or tenant groups); and, share data associated with a first microservice to a second microservice of the domain. Such sharing may be based on the communication of an encryption key, used to encrypt the data in memory, from a proxy (such as a sidecar) associated with the first microservice to a proxy associated with the second microservice; and maintaining the encrypted data within the memory, for use with the second microservice, as accessible with the communicated encryption key.


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