The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Jul. 02, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Cheng-Ming Lin, Kaohsiung, TW;

Kai Tak Lam, Hsinchu, TW;

Sai-Hooi Yeong, Hsinchu County, TW;

Chi On Chui, Hsinchu, TW;

Ziwei Fang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/00 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 21/28 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 29/516 (2013.01); H01L 21/28088 (2013.01); H01L 21/76829 (2013.01); H01L 29/40111 (2019.08); H01L 29/4966 (2013.01); H01L 29/517 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7851 (2013.01);
Abstract

A semiconductor structure that includes a semiconductor fin disposed over a substrate, S/D features disposed over the semiconductor fin, and a metal gate stack interposed between the S/D features. The metal gate stack includes a gate dielectric layer disposed over the semiconductor fin, a capping layer disposed over the gate dielectric layer, and a gate electrode disposed over the capping layer, where the gate dielectric layer includes hafnium oxide with hafnium atoms and oxygen atoms arranged in a Pca2space group.


Find Patent Forward Citations

Loading…