The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Sep. 04, 2019
Applicant:

Kioxia Corporation, Minato-ku, JP;

Inventors:

Shinichi Sotome, Yokkaichi, JP;

Tatsufumi Hamada, Nagoya, JP;

Yasuhiro Uchimura, Yokkaichi, JP;

Tomohiro Kuki, Yokkaichi, JP;

Assignee:

KIOXIA CORPORATION, Minato-ku, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 23/481 (2013.01); H01L 27/1157 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes a base layer, conductive layers, an insulation layer, a semiconductor layer and a charge storage layer. The conductive layers are stacked above the base layer in a first direction. The insulation layer is extending in the conductive layers in the first direction. The semiconductor layer is arranged between the insulation layer and the conductive layers. The charge storage layer is arranged between the semiconductor layer and the conductive layers. The insulation layer includes a first insulation layer arranged on a side of the base layer and containing polysilazane and a second insulation layer arranged on the first insulation layer on a side opposite from the base layer.


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