The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Feb. 21, 2019
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Chia-Jung Hsu, Hsinchu County, TW;

Wein-Town Sun, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11519 (2017.01); H01L 27/11517 (2017.01); G11C 16/04 (2006.01); G11C 16/12 (2006.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11524 (2017.01); H01L 49/02 (2006.01); H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/788 (2006.01); H01L 27/1156 (2017.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11519 (2013.01); G11C 16/0416 (2013.01); G11C 16/0433 (2013.01); G11C 16/10 (2013.01); G11C 16/12 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 27/1156 (2013.01); H01L 27/11517 (2013.01); H01L 27/11524 (2013.01); H01L 28/40 (2013.01); H01L 29/1095 (2013.01); H01L 29/42324 (2013.01); H01L 29/42328 (2013.01); H01L 29/788 (2013.01); H01L 29/7885 (2013.01); G11C 2216/04 (2013.01); H01L 29/4916 (2013.01);
Abstract

An erasable programmable non-volatile memory includes a first select transistor, a first floating gate transistor, a second select transistor and a second floating gate transistor. A select gate and a first source/drain terminal of the first select transistor receive a first select gate voltage and a first source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the first floating gate transistor are connected with a second source/drain terminal of the first select transistor and a first bit line voltage, respectively. A select gate and a first source/drain terminal of the second select transistor receive a second select gate voltage and a second source line voltage, respectively. A first source/drain terminal and a second source/drain terminal of the second floating gate transistor are connected with the second source/drain terminal of the second select transistor and a second bit line voltage, respectively.


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