The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Mar. 05, 2020
Applicant:

Sandisk Technologies Llc, Addison, TX (US);

Inventors:

Yoshitaka Otsu, Yokkaichi, JP;

Masanori Terahara, Yokkaichi, JP;

Junpei Kanazawa, Yokkaichi, JP;

Assignee:

SANDISK TECHNOLOGIES LLC, Addison, TX (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 23/522 (2006.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 27/11565 (2017.01); H01L 27/11556 (2017.01); H01L 29/66 (2006.01); H01L 27/11519 (2017.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 27/11524 (2017.01);
U.S. Cl.
CPC ...
H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 27/0886 (2013.01); H01L 27/1157 (2013.01); H01L 27/11519 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 27/11565 (2013.01); H01L 27/11582 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01);
Abstract

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, a perforated dielectric moat structure vertically extending through the alternating stack, and an interconnection via structure laterally surrounded by the perforated dielectric moat structure and vertically extending through each insulating layer within the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of memory elements located at levels of the electrically conductive layers. The perforated dielectric moat structure includes a plurality of lateral openings at each level of the insulating layers, and does not include any opening at levels of the electrically conductive layers. An interconnection via structure can be laterally surrounded by the perforated dielectric moat structure, and can vertically extend through each insulating layer within the alternating stack.


Find Patent Forward Citations

Loading…