The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Oct. 22, 2019
Applicant:

Obsidian Sensors, Inc., San Diego, CA (US);

Inventors:

Yaoling Pan, San Diego, CA (US);

Tallis Young Chang, San Diego, CA (US);

John Hyunchul Hong, San Diego, CA (US);

Assignee:

Obsidian Sensors, Inc., San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/31 (2006.01); B81C 1/00 (2006.01); B81B 7/00 (2006.01); H01L 21/56 (2006.01); H01L 21/683 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 27/12 (2006.01); H01L 33/52 (2010.01); H01L 33/62 (2010.01); H01L 51/00 (2006.01); H01L 51/52 (2006.01); H01L 51/56 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3121 (2013.01); B81B 7/0058 (2013.01); B81C 1/00238 (2013.01); B81C 1/00301 (2013.01); H01L 21/568 (2013.01); H01L 21/6835 (2013.01); H01L 21/76898 (2013.01); H01L 23/3135 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/124 (2013.01); H01L 33/52 (2013.01); H01L 33/62 (2013.01); H01L 51/003 (2013.01); H01L 51/5203 (2013.01); H01L 51/5253 (2013.01); H01L 51/56 (2013.01); B81C 2203/0145 (2013.01); B81C 2203/0785 (2013.01); B81C 2203/0792 (2013.01); H01L 2933/005 (2013.01); H01L 2933/0066 (2013.01);
Abstract

This disclosure provides devices and methods for 3-D device packaging with backside interconnections. One or more device elements can be hermetically sealed from an ambient environment, such as by vacuum lamination and bonding. One or more via connections provide electrical interconnection from a device element to a back side of a device substrate, and provide electrical interconnection from the device substrate to external circuitry on the back side of the device. The external circuitry can include a printed circuit board or flex circuit. In some implementations, an electrically conductive pad is provided on the back side, which is electrically connected to at least one of the via connections. In some implementations, the one or more via connections are electrically connected to one or more electrical components or interconnections, such as a TFT or a routing line.


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