The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 22, 2022

Filed:

Mar. 15, 2021
Applicant:

Kioxia Corporation, Tokyo, JP;

Inventors:

Reika Tanaka, Yokohama, JP;

Masumi Saitoh, Yokkaichi, JP;

Takashi Maeda, Kamakura, JP;

Rieko Funatsuki, Yokohama, JP;

Hidehiro Shiga, Yokohama, JP;

Assignee:

Kioxia Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/22 (2006.01); H01L 27/11597 (2017.01);
U.S. Cl.
CPC ...
G11C 11/2275 (2013.01); G11C 11/223 (2013.01); G11C 11/2273 (2013.01); G11C 11/2277 (2013.01); H01L 27/11597 (2013.01);
Abstract

According to one embodiment, a memory device includes: a third layer between first and a second layers above a substrate; a pillar being adjacent to the first to third layers and including a ferroelectric layer; a memory cell between the third layer and the pillar; and a circuit which executes a first operation for a programming, a second operation for an erasing using a first voltage, and a third operation of applying a second voltage between the third layer and the pillar. The first voltage has a first potential difference, the second voltage has a second potential difference smaller than the first potential difference. A potential of the third conductive layer is lower than a potential of the pillar in each of the first and second voltages. The third operation is executed between the first operation and the second operation.


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