Arrays of memory cells and methods of forming an array of vertically stacked tiers of memory cells

Abstract

An array of vertically stacked tiers of memory cells includes a plurality of horizontally oriented access lines within individual tiers of memory cells and a plurality of horizontally oriented global sense lines elevationally outward of the tiers. A plurality of select transistors is elevationally inward of the tiers. A plurality of pairs of local first and second vertical lines extends through the tiers. The local first vertical line within individual of the pairs is in conductive connection with one of the global sense lines and in conductive connection with one of the two source/drain regions of one of the select transistors. The local second vertical line within individual of the pairs is in conductive connection with another of the two source/drain regions of the one select transistor. Individual of the memory cells include a crossing one of the local second vertical lines and one of the horizontal access lines and programmable material there-between. Other aspects and implementations, including methods, are disclosed.