The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Aug. 08, 2019
Applicants:

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Rongyao Chang, Shanghai, CN;

Zhuofan Chen, Shanghai, CN;

Haiyang Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01); H01L 29/792 (2006.01); H01L 27/11526 (2017.01); H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 27/105 (2006.01); H01L 27/11521 (2017.01); H01L 27/11546 (2017.01); H01L 27/11551 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11526 (2013.01); H01L 27/1052 (2013.01); H01L 27/11521 (2013.01); H01L 27/11546 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/7889 (2013.01); H01L 29/7923 (2013.01); H01L 29/7926 (2013.01);
Abstract

A flash memory device and its manufacturing method, which is related to semiconductor techniques. The flash memory device comprises: a substrate; and a memory unit on the substrate, comprising: a channel structure on the substrate, wherein the channel structure comprise, in an order from inner to outer of the channel structure, a channel layer, an insulation layer wrapped around the channel layer, and a charge capture layer wrapped around the insulation layer; a plurality of gate structures wrapped around the channel structure and arranged along a symmetry axis of the channel structure, wherein there exist cavities between neighboring gate structures; a support structure supporting the gate structures; and a plurality of gate contact components each contacting a gate structure. The cavities between neighboring gate structures lower the parasitic capacitance, reduce inter-gate interference, and suppress the influence from writing or erasing operations of nearby memory units.


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