The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Nov. 21, 2018
Applicant:

Csmc Technologies Fab2 Co., Ltd., Jiangsu, CN;

Inventors:

Shikang Cheng, Wuxi New District, CN;

Yan Gu, Wuxi New District, CN;

Sen Zhang, Wuxi New District, CN;

Assignee:

CSMC TECHNOLOGIES FAB2 CO., LTD., Wuxi New District, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0883 (2013.01); H01L 29/7802 (2013.01);
Abstract

The present application provides an integrated semiconductor device and an electronic apparatus, comprising a semiconductor substrate and a first doped epitaxial layer having a first region, a second region, and a third region; a partition structure is arranged in the third region; the first region is formed having at least two second doped deep wells, and the second region is formed having at least two second doped deep wells; a dielectric island partially covers a region between two adjacent doped deep wells in the first region and second region; a gate structure covers the dielectric island; a first doped source region is located on the two sides of the gate structure, and a first doped source region located in the same second doped deep well is separated; a first doped trench is located on the two sides of the dielectric island in the first region, and extends laterally to the first doped source region.


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