The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Jun. 30, 2020
Applicant:

Micron Technology, Inc., Boise, ID (US);

Inventor:

Kevin J. Torek, Meridian, ID (US);

Assignee:

Micron Technology, Inc., Boise, ID (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/84 (2006.01); H01L 21/8238 (2006.01); H01L 29/66 (2006.01); H01L 27/088 (2006.01); H01L 29/08 (2006.01); H01L 29/10 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 21/822 (2006.01); H01L 27/06 (2006.01); H01L 27/108 (2006.01); H01L 21/02 (2006.01); H01L 21/308 (2006.01);
U.S. Cl.
CPC ...
H01L 21/823885 (2013.01); H01L 21/02565 (2013.01); H01L 21/308 (2013.01); H01L 21/8221 (2013.01); H01L 21/823828 (2013.01); H01L 21/84 (2013.01); H01L 27/0688 (2013.01); H01L 27/088 (2013.01); H01L 27/10814 (2013.01); H01L 27/10873 (2013.01); H01L 27/10897 (2013.01); H01L 29/0847 (2013.01); H01L 29/1033 (2013.01); H01L 29/42384 (2013.01); H01L 29/66742 (2013.01); H01L 29/7869 (2013.01); H01L 29/78618 (2013.01); H01L 29/78642 (2013.01); H01L 29/78696 (2013.01);
Abstract

A method of forming a semiconductor structure comprises forming an array of vertical thin film transistors. Forming the array of vertical thin film transistors comprises forming a source region, forming a channel material comprising an oxide semiconductor material over the source region, exposing the channel material to a dry etchant comprising hydrogen bromide to pattern the channel material into channel regions of adjacent vertical thin film transistor structures, forming a gate dielectric material on sidewalls of the channel regions, forming a gate electrode material adjacent to the gate dielectric material, and forming a drain region over the channel regions. Related methods of forming semiconductor structures and an array of memory cells are also disclosed.


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