Apparatuses and methods for clock leveling in semiconductor memories

Abstract

Apparatuses and methods for clock leveling in semiconductor memory are disclosed. In an example apparatus, a latency control circuit is configured to provide in first and second modes an active first control signal having a timing based on latency information and a system clock. A clock leveling control circuit is configured to provide in the first mode an active second control signal responsive to an active first control signal at a clock transition of a first clock and further configured to provide in the second mode clock leveling feedback responsive to the active first control signal at a transition of a second clock. A read clock circuit is configured to provide the multiphase clocks responsive to the active second control signal. A serializer circuit configured to serialize the data based on the multiphase clocks from the read clock circuit to provide the data in series.