The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

May. 31, 2018
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Martin Langhammer, Alderbury, GB;

Sudarshan Srinivasan, Bangalore, IN;

Gregg William Baeckler, San Jose, CA (US);

Duncan Moss, Hillsboro, OR (US);

Sasikanth Avancha, Bangalore, IN;

Dipankar Das, Pune, IN;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06N 3/08 (2006.01); G06N 3/04 (2006.01); G06N 3/063 (2006.01); G06F 17/16 (2006.01); G06F 7/501 (2006.01); G06F 5/01 (2006.01); G06F 7/509 (2006.01); H03M 7/40 (2006.01); H03M 7/42 (2006.01); H03M 7/30 (2006.01);
U.S. Cl.
CPC ...
G06N 3/08 (2013.01); G06F 5/01 (2013.01); G06F 7/501 (2013.01); G06F 7/509 (2013.01); G06F 17/16 (2013.01); G06N 3/04 (2013.01); G06N 3/0454 (2013.01); G06N 3/0481 (2013.01); G06N 3/063 (2013.01); H03M 7/4006 (2013.01); H03M 7/42 (2013.01); H03M 7/6011 (2013.01); H03M 7/30 (2013.01);
Abstract

The present disclosure relates generally to techniques for improving the implementation of certain operations on an integrated circuit. In particular, deep learning techniques, which may use a deep neural network (DNN) topology, may be implemented more efficiently using low-precision weights and activation values by efficiently performing down conversion of data to a lower precision and by preventing data overflow during suitable computations. Further, by more efficiently mapping multipliers to programmable logic on the integrated circuit device, the resources used by the DNN topology to perform, for example, inference tasks may be reduced, resulting in improved integrated circuit operating speeds.


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