The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 15, 2022

Filed:

Dec. 03, 2018
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Mitchell G. Poplack, San Jose, CA (US);

Yuhei Hayashi, San Jose, CA (US);

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); H04L 49/101 (2022.01); H04L 45/00 (2022.01); G06F 13/10 (2006.01); G06F 13/38 (2006.01);
U.S. Cl.
CPC ...
G06F 9/45504 (2013.01); G06F 13/105 (2013.01); H04L 45/04 (2013.01); H04L 49/101 (2013.01); G06F 13/385 (2013.01);
Abstract

The embodiments disclosed herein describe a switching ASIC that provides a dynamic single-bit routing and multiplexing function in an emulation system. The switching ASIC may receive a set of incoming data streams from a first set of emulation devices (e.g., emulation ASICs), disassemble each data stream to the constituent bits, dynamically multiplex the bits, reassemble the multiplexed bits into outgoing data streams, and transmit the outgoing data streams to a second set of emulation devices. Multiple statically scheduled selection tables (UCSWs), one for each output lane of the switching ASIC, drive the selection and routing of bits from input slots of various input lanes to the output slots of the output lane.


Find Patent Forward Citations

Loading…