The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Sep. 04, 2020
Applicant:

Cadence Design Systems, Inc., San Jose, CA (US);

Inventors:

Vineeth Anavangot, Bangalore, IN;

Maitri Misra, Kolkata, IN;

Rajesh Cheeranthodi, Bangalore, IN;

Assignee:

CADENCE DESIGN SYSTEMS, INC., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 25/03 (2006.01); H03K 17/687 (2006.01);
U.S. Cl.
CPC ...
H04L 25/03057 (2013.01); H03K 17/6872 (2013.01);
Abstract

In some examples, a receiver can include a sampler circuit that can be configured to process a data input signal corresponding to a current bit received at a receiver based on a capacitive weighted signal to compensate for distortion effects that a previously received bit at the receiver has on the data input signal. The receiver can include a capacitive coupling feedback circuit that can be configured to generate the capacitive weighted signal corresponding to a weighted detected bit of the previously received bit based on a capacitance of a subset of capacitors of a plurality of capacitors of the feedback circuit. The capacitive coupling feedback circuit can be configured to selectively control a number of capacitors of the plurality of capacitors that are connected in parallel corresponding to the subset of capacitors to control an amount of weight applied to the detected bit to generate the capacitive weighted signal.


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