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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 11271114 B1

PDFFull Text
Date of Patent:
Mar. 08, 2022

Filed:

Jun. 01, 2020

Strained gate semiconductor device with oxygen-doped interlayer dielectric material

Applicant:

Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu, TW;

Inventors:

Cheng-Ta Wu, Chiayi County, TW;

Chii-Ming Wu, Taipei, TW;

Shiu-Ko Jangjian, Tainan, TW;

Kun-Tzu Lin, Tainan, TW;

Lan-Fang Chang, Yunlin County, TW;

Assignee:

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu, TW;

Attorney:

Hauptman Ham, LLP

Primary Examiner:

Younes Boulghassoul

Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/423 (2006.01); H01L 21/02 (2006.01); H01L 27/092 (2006.01); H01L 21/3115 (2006.01); H01L 29/66 (2006.01); H01L 21/8238 (2006.01); H01L 21/28 (2006.01); H01L 21/8234 (2006.01); H01L 29/40 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/02321 (2013.01); H01L 21/02323 (2013.01); H01L 21/28114 (2013.01); H01L 21/28158 (2013.01); H01L 21/3115 (2013.01); H01L 21/31155 (2013.01); H01L 21/823456 (2013.01); H01L 21/823821 (2013.01); H01L 27/0924 (2013.01); H01L 29/401 (2013.01); H01L 29/42364 (2013.01); H01L 29/42376 (2013.01); H01L 29/512 (2013.01); H01L 29/66545 (2013.01); H01L 29/66795 (2013.01); H01L 29/7843 (2013.01); H01L 29/7851 (2013.01); H01L 29/495 (2013.01); H01L 29/513 (2013.01);
Abstract

A semiconductor device includes a gate stack over a substrate. The semiconductor device further includes an interlayer dielectric (ILD) at least partially enclosing the gate stack. The ILD includes a first portion doped with an oxygen-containing material. The ILD further includes a second portion doped with a large species material, wherein the second portion includes a first sidewall substantially perpendicular to a top surface of the substrate, and the second portion includes a second sidewall having a positive angle with respect to the first sidewall.

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