The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

May. 06, 2020
Applicant:

United Microelectronics Corp., Hsin-Chu, TW;

Inventors:

Chia-Ming Kuo, Kaohsiung, TW;

Fu-Jung Chuang, Kaohsiung, TW;

Po-Jen Chuang, Kaohsiung, TW;

Chia-Wei Chang, Tainan, TW;

Guan-Wei Huang, Tainan, TW;

Chia-Yuan Chang, Kaohsiung, TW;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 21/28 (2006.01); H01L 29/78 (2006.01); H01L 21/3105 (2006.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 29/6659 (2013.01); H01L 21/28176 (2013.01); H01L 21/3105 (2013.01); H01L 29/785 (2013.01); H01L 29/7833 (2013.01); H01L 21/2652 (2013.01);
Abstract

A method for fabricating a semiconductor device includes the steps of: providing a substrate having a NMOS region and a PMOS region; forming a first gate structure on the NMOS region and a second gate structure on the PMOS region; forming a seal layer on the first gate structure and the second gate structure; forming a first lightly doped drain (LDD) adjacent to the first gate structure; forming a second LDD adjacent to the second gate structure; and performing a soak anneal process to boost an oxygen concentration of the seal layer for reaching a saturation level.


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