The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 08, 2022

Filed:

Sep. 15, 2020
Applicant:

Taiwan Semiconductor Manufacturing Company Ltd., Hsinchu, TW;

Inventors:

Chia Hao Tu, Tainan, TW;

Hsueh-Chih Chou, Tainan, TW;

Sang Hoo Dhong, Hsinchu, TW;

Jerry Chang Jui Kao, Taipei, TW;

Chi-Lin Liu, New Taipei, TW;

Cheng-Chung Lin, Hsinchu, TW;

Shang-Chih Hsieh, Taoyuan County, TW;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 1/14 (2006.01);
U.S. Cl.
CPC ...
G06F 30/3312 (2020.01); G06F 1/14 (2013.01);
Abstract

A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.


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