The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Apr. 01, 2016
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Patrick Morrow, Portland, OR (US);

Rishabh Mehandru, Portland, OR (US);

Nathan D. Jack, Forest Grove, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/08 (2006.01); H01L 29/739 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/165 (2006.01); H01L 27/02 (2006.01); H01L 29/861 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01); H01L 21/762 (2006.01); H01L 21/84 (2006.01); H01L 23/00 (2006.01); H01L 29/786 (2006.01); H01L 29/20 (2006.01); H01L 29/205 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); H01L 21/76256 (2013.01); H01L 21/84 (2013.01); H01L 24/03 (2013.01); H01L 24/05 (2013.01); H01L 24/13 (2013.01); H01L 27/0255 (2013.01); H01L 27/0629 (2013.01); H01L 28/00 (2013.01); H01L 29/06 (2013.01); H01L 29/0657 (2013.01); H01L 29/08 (2013.01); H01L 29/165 (2013.01); H01L 29/66356 (2013.01); H01L 29/7391 (2013.01); H01L 29/78603 (2013.01); H01L 29/78606 (2013.01); H01L 29/861 (2013.01); H01L 29/20 (2013.01); H01L 29/2003 (2013.01); H01L 29/205 (2013.01);
Abstract

Integrated circuit (IC) strata including one or more transistor and one or more semiconductor diode. A transistor may include one or more non-planar semiconductor bodies in which there is a channel region while the diode also includes one or more non-planar semiconductor bodies in which there is a p-type region, an n-type region, or both. One IC stratum may be only hundreds of nanometers in thickness and include both front-side and back-side interconnect levels. The front-side interconnect level is disposed over a front side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the transistor. The back-side interconnect level is disposed over a back side of one or more of the non-planar semiconductor bodies and is coupled to at least one terminal of the semiconductor diode.


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