The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Nov. 13, 2019
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;

Inventors:

Meng-Han Lin, Hsinchu, TW;

Chih-Ren Hsieh, Changhua, TW;

Ya-Chen Kao, Fuxing Township, TW;

Chen-Chin Liu, Hsinchu, TW;

Chih-Pin Huang, Hsinchu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11529 (2017.01); H01L 27/11524 (2017.01); H01L 27/11526 (2017.01); H01L 29/423 (2006.01); H01L 27/11519 (2017.01); H01L 21/66 (2006.01);
U.S. Cl.
CPC ...
H01L 22/34 (2013.01); H01L 27/11524 (2013.01); H01L 27/11526 (2013.01); H01L 27/11529 (2013.01); H01L 29/42328 (2013.01); H01L 27/11519 (2013.01);
Abstract

Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.


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