The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 01, 2022
Filed:
Mar. 05, 2018
Applicant:
Intel Corporation, Santa Clara, CA (US);
Inventors:
Bruce Querbach, Hillsboro, OR (US);
Christopher Connor, Hillsboro, OR (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/56 (2006.01); G11C 13/00 (2006.01); G11C 11/408 (2006.01); H03K 19/0175 (2006.01); G11C 14/00 (2006.01); G11C 29/12 (2006.01); G11C 7/16 (2006.01); G11C 7/06 (2006.01); G11C 27/00 (2006.01); G11C 29/02 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 13/004 (2013.01); G11C 7/06 (2013.01); G11C 7/16 (2013.01); G11C 11/4082 (2013.01); G11C 11/56 (2013.01); G11C 11/5642 (2013.01); G11C 11/5678 (2013.01); G11C 11/5685 (2013.01); G11C 13/0004 (2013.01); G11C 14/0045 (2013.01); G11C 27/005 (2013.01); G11C 29/12 (2013.01); H03K 19/0175 (2013.01); G11C 29/021 (2013.01); G11C 29/028 (2013.01); G11C 2013/0042 (2013.01); G11C 2029/0409 (2013.01); G11C 2029/0411 (2013.01); G11C 2029/1204 (2013.01); G11C 2213/71 (2013.01);
Abstract
An embodiment of a semiconductor apparatus may include technology to convert an analog voltage level of a memory cell of a multi-level memory to a multi-bit digital value, and determine a single-bit value of the memory cell based on the multi-bit digital value. Some embodiments may also include technology to track a temporal history of accesses to the memory cell for a duration in excess of ten seconds, and determine the single-bit value of the memory cell based on the multi-bit digital value and the temporal history. Other embodiments are disclosed and claimed.