The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 01, 2022

Filed:

Jun. 24, 2020
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Prasoonkumar Surti, Folsom, CA (US);

Carsten Benthin, Voelklingen, DE;

Karthik Vaidyanathan, San Francisco, CA (US);

Philip Laws, Santa Clara, CA (US);

Scott Janus, Loomis, CA (US);

Sven Woop, Völklingen, DE;

Assignee:

INTEL CORPORATION, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 15/00 (2011.01); G06T 15/06 (2011.01);
U.S. Cl.
CPC ...
G06T 15/005 (2013.01); G06T 15/06 (2013.01); G06T 2210/52 (2013.01);
Abstract

Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.


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