The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2022
Filed:
Mar. 30, 2018
Intel Corporation, Santa Clara, CA (US);
Niranjan Karandikar, Chandler, AZ (US);
Wayne Ballantyne, Chandler, AZ (US);
Gregory Chance, Chandler, AZ (US);
Simon Hughes, Chandler, AZ (US);
Daniel Schwartz, Scottsdale, AZ (US);
Nebil Tanzi, Hoffman Estates, IL (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
Techniques are provided for reducing or mitigating phase noise of a digital phase lock loop or the system depending on the digital phase lock loop. In an example, a multiple-mode digital phase lock loop can include a digital phase lock loop (DPLL), multiple frequency scalers configured to receive a reference clock, and a multiplexer configured to receive a mode command signal and to couple an output of one of the multiple frequency scalers to an input of the DPLL in response to a state of the mode command signal.