The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Mar. 13, 2020
Applicants:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Semiconductor Manufacturing International (Beijing) Corporation, Beijing, CN;

Inventors:

Yang Hu, Shanghai, CN;

Jun Wang, Shanghai, CN;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/08 (2006.01); H01L 21/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66575 (2013.01); H01L 29/0847 (2013.01); H01L 29/6653 (2013.01); H01L 29/6656 (2013.01); H01L 21/02532 (2013.01);
Abstract

A semiconductor structure and forming method are provided. The method includes providing a substrate, forming a gate structure over the substrate, forming a first spacer on a sidewall of the gate structure; forming an epitaxial layer on both sides of the gate structure and the first spacer, a surface of the epitaxial layer is higher than a surface of the substrate; forming a dielectric layer on the epitaxial layer and on surface of the first spacer, the dielectric layer is formed on both sides of the gate structure; after forming the dielectric layer, removing the first spacer to form a first opening between the epitaxial layer and the gate structure and between the dielectric layer and the gate structure, and in the first opening forming a second spacer that has a gap between the epitaxial layer and the gate structure.


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