The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 22, 2022

Filed:

Oct. 03, 2019
Applicant:

Winbond Electronics Corp., Taichung, TW;

Inventors:

Yasuhiro Tomita, Taichung, TW;

Chi Shun Lin, Fremont, CA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/24 (2006.01); H01L 23/528 (2006.01); H01L 23/522 (2006.01); H01L 45/00 (2006.01); G11C 13/00 (2006.01);
U.S. Cl.
CPC ...
H01L 27/2463 (2013.01); G11C 13/004 (2013.01); G11C 13/0007 (2013.01); G11C 13/0069 (2013.01); G11C 13/0097 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 27/2436 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01); G11C 2013/005 (2013.01); G11C 2013/009 (2013.01); G11C 2213/32 (2013.01); G11C 2213/79 (2013.01);
Abstract

The invention provides a resistive memory with better area efficiency without degrading reliability, which includes an array area, word lines, a local bit line, source lines, and a shared bit line. In the array area, memory cells are arranged in a matrix, and each memory cells includes a variable resistance element and an accessing transistor. The word lines extend in a row direction of the array area and are connected to the memory cells in the row direction. The local bit line extends in a column direction of the array area. The source lines extend in the column direction and are connected to first electrodes of the memory cells in the column direction. The shared bit line is connected to the local bit line. The shared bit line extends in the row direction and is connected to second electrodes of the memory cells in the row direction.


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