The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 22, 2022
Filed:
Jun. 30, 2020
Cadence Design Systems, Inc., San Jose, CA (US);
Sourav Kumar Sircar, Noida, IN;
Marc Heyberger, Mandelieu, FR;
Manish Garg, Greater Noida, IN;
Akash Khandelwal, Fremont, CA (US);
Chunlong Pan, Fremont, CA (US);
Ruchir Agarwal, Noida, IN;
Anurag Saran, Noida, IN;
Lalit Bharat, Greater Noida, IN;
Namrata M Sadhankar, Noida, IN;
Manish Bhatia, Ghaziabad, IN;
Renuka Deshpande, Noida, IN;
Cadence Design Systems, Inc., San Jose, CA (US);
Abstract
Disclosed are methods, systems, and articles of manufacture for implementing an electronic design with high-capacity design closure. A reduced netlist may be generated for an analysis view of an electronic design based at least in part upon logic of interest in the analysis view. A closure may be performed based at least in part upon a union netlist, wherein the union netlist is generated from the reduced netlist. The electronic design may then be implemented based at least in part upon a result of the closure task.