The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Feb. 23, 2017
Applicants:

Centre National DE LA Recherche Scientifique, Paris, FR;

Universite Claude Bernard Lyon 1, Villeurbanne, FR;

Soitec, Bernin, FR;

Inventors:

Christophe Figuet, Crolles, FR;

Oleg Kononchuk, Theys, FR;

Kassam Alassaad, Villeurbanne, FR;

Gabriel Ferro, Villeurbanne, FR;

Véronique Souliere, Saint Marcel Bel Accueil, FR;

Christelle Veytizou, Bernin, FR;

Taguhi Yeghoyan, Bourgoin-Jallieu, FR;

Assignees:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 29/16 (2006.01);
U.S. Cl.
CPC ...
H01L 29/06 (2013.01); H01L 21/0245 (2013.01); H01L 21/0259 (2013.01); H01L 21/0262 (2013.01); H01L 21/02444 (2013.01); H01L 21/02447 (2013.01); H01L 21/02507 (2013.01); H01L 21/02595 (2013.01); H01L 21/7624 (2013.01); H01L 21/76254 (2013.01); H01L 29/1608 (2013.01);
Abstract

A support for a semiconductor structure includes a charge-trapping layer on a base substrate. The charge-trapping layer consists of a polycrystalline main layer and, interposed in the main layer or between the main layer and the base substrate, at least one intermediate polycrystalline layer composed of a silicon and carbon alloy or carbon. The intermediate layer has a resistivity greater than 1000 ohm·cm.


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