The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Sep. 03, 2019
Applicant:

Toshiba Memory Corporation, Tokyo, JP;

Inventors:

Ken Komiya, Nagoya Aichi, JP;

Takashi Ishida, Yokkaichi Mie, JP;

Hiroshi Kanno, Yokkaichi Mie, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11524 (2017.01); H01L 27/11556 (2017.01); H01L 21/74 (2006.01); H01L 29/10 (2006.01); H01L 27/1157 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/743 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11556 (2013.01); H01L 29/1083 (2013.01); H01L 29/1087 (2013.01);
Abstract

A semiconductor memory device includes a substrate, gate electrodes arranged in a thickness direction of the substrate, first and second semiconductor layers, a gate insulating film, and a first contact. The first semiconductor layer extends in the thickness direction and faces the gate electrodes. The gate insulating film is between the gate electrodes and the first semiconductor layer. The second semiconductor layer is between the substrate and the gate electrodes and connected to a side surface of the first semiconductor layer in a surface direction. The first contact extends in the thickness direction and electrically connected to the second semiconductor layer. The second semiconductor layer includes a first region in contact with the side surface of the first semiconductor layer and containing P-type impurities, and a first contact region electrically connected to the first contact and having a higher concentration of N-type impurities than the first region.


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