The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 15, 2022
Filed:
Mar. 29, 2021
Sambanova Systems, Inc., Palo Alto, CA (US);
Tejas Nagendra Babu Nama, Sunnyvale, CA (US);
Ruddhi Arun Chaphekar, Santa Clara, CA (US);
Ram Sivaramakrishnan, San Jose, CA (US);
Raghu Prabhakar, San Jose, CA (US);
Sumti Jairath, Santa Clara, CA (US);
Junjue Wang, San Mateo, CA (US);
Kaizhao Liang, Palo Alto, CA (US);
Adi Fuchs, West Windsor, NJ (US);
Matheen Musaddiq, Austin, TX (US);
Arvind Sujeeth, San Francisco, CA (US);
SambaNova Systems, Inc., Palo Alto, CA (US);
Abstract
Disclosed is a data processing system which includes compile time logic configured to section a graph into a sequence of subgraphs, the sequence of subgraphs including at least a first subgraph. The compile time logic configures the first subgraph to generate a plurality of output tiles of an output tensor. A runtime logic configured with the compile time logic is to execute the sequence of subgraphs to generate, at the output of the first subgraph, the plurality of output tiles of the output tensor, and write the plurality of output tiles in a memory in an overlapping configuration. In an example, an overlapping region between any two neighboring output tiles of the plurality of output tiles comprises a summation of a corresponding region of a first neighboring output tile and a corresponding region of a second neighboring output tile.