The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 15, 2022

Filed:

Dec. 22, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Stephen Palermo, Chandler, AZ (US);

Gerald Rogers, Chandler, AZ (US);

Shih-Wei Chien, Shanghai, CN;

Namakkal Venkatesan, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/455 (2018.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01); G06F 12/0815 (2016.01); G06F 12/0875 (2016.01); G06F 12/0811 (2016.01); G06F 9/50 (2006.01); G06F 9/38 (2018.01);
U.S. Cl.
CPC ...
G06F 9/45558 (2013.01); G06F 9/3877 (2013.01); G06F 9/45529 (2013.01); G06F 9/50 (2013.01); G06F 12/0811 (2013.01); G06F 12/0815 (2013.01); G06F 12/0875 (2013.01); G06F 13/1668 (2013.01); G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 13/4068 (2013.01); G06F 13/4282 (2013.01); G06F 2009/4557 (2013.01); G06F 2009/45579 (2013.01); G06F 2009/45595 (2013.01); G06F 2213/0026 (2013.01); G06F 2213/0058 (2013.01); G06F 2213/0064 (2013.01);
Abstract

A computer system may comprise a multi-chip package (MCP), which includes multi-core processor circuitry and hardware accelerator circuitry. The multi-core processor circuitry may comprise a plurality of processing cores, and the hardware accelerator circuitry may be coupled with the multi-core processor circuitry via one or more coherent interconnects and one or more non-coherent interconnects. A coherency domain of the MCP may be extended to encompass the hardware accelerator circuitry, or portions thereof An interconnect selection module may select an individual coherent interconnect or an individual non-coherent interconnect based on application requirements of an application to be executed and a workload characteristic policy. Other embodiments are described and/or claimed.


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