The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Sep. 30, 2020
Applicant:

Ememory Technology Inc., Hsin-Chu, TW;

Inventors:

Hsueh-Wei Chen, Hsinchu County, TW;

Wei-Ren Chen, Hsinchu County, TW;

Wein-Town Sun, Hsinchu County, TW;

Assignee:

EMEMORY TECHNOLOGY INC., Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/105 (2006.01); H01L 29/06 (2006.01); H01L 29/792 (2006.01); G11C 16/34 (2006.01); H01L 29/423 (2006.01); G11C 16/04 (2006.01); H01L 27/11563 (2017.01); G11C 16/10 (2006.01); G11C 16/14 (2006.01); G11C 16/26 (2006.01); H01L 27/11524 (2017.01); H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
H01L 29/0653 (2013.01); G11C 16/0425 (2013.01); G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); G11C 16/34 (2013.01); H01L 27/11524 (2013.01); H01L 27/11563 (2013.01); H01L 29/4234 (2013.01); H01L 29/7885 (2013.01); H01L 29/792 (2013.01);
Abstract

A non-volatile memory includes a substrate region, a barrier layer, an N-type well region, an isolation structure, a first gate structure, a first sidewall insulator, a first P-type doped region, a second P-type doped region and an N-type doped region. The isolation structure is arranged around the N-type well region and formed over the barrier layer. The N-type well region is surrounded by the isolation structure and the barrier layer. Consequently, the N-type well region is an isolation well region. The first gate structure is formed over a surface of the N-type well region. The first sidewall insulator is arranged around the first gate structure. The first P-type doped region, the second P-type doped region and the N-type doped region are formed under the surface of the N-type well region.


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