The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Aug. 29, 2019
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Ju-Youn Choi, Hwaseong-si, KR;

Eun-Seok Song, Hwaseong-si, KR;

Seung-Yong Cha, Hwaseong-si, KR;

Yun-Hee Lee, Hwaseong-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/538 (2006.01); H01F 27/28 (2006.01); H01F 27/24 (2006.01); H01L 25/065 (2006.01); H01F 17/00 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01F 17/0006 (2013.01); H01F 27/24 (2013.01); H01F 27/2804 (2013.01); H01L 23/5383 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H01F 2017/0066 (2013.01); H01F 2017/0073 (2013.01); H01L 23/49816 (2013.01); H01L 23/5381 (2013.01); H01L 23/5385 (2013.01); H01L 24/16 (2013.01); H01L 2224/16145 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/16235 (2013.01); H01L 2224/17181 (2013.01); H01L 2225/0652 (2013.01); H01L 2225/06517 (2013.01); H01L 2225/06541 (2013.01); H01L 2225/06548 (2013.01); H01L 2225/06586 (2013.01); H01L 2924/14 (2013.01); H01L 2924/1427 (2013.01); H01L 2924/1432 (2013.01); H01L 2924/1434 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01); H01L 2924/19011 (2013.01); H01L 2924/19041 (2013.01); H01L 2924/19042 (2013.01);
Abstract

An electronic device package includes a package substrate, an interposer located above the package substrate and electrically connected to the package substrate, a processing device located above the interposer and electrically connected to the interposer, at least one high bandwidth memory device located above the interposer and electrically connected to the interposer and the processing device, a power management integrated circuit device located above the interposer and electrically connected to the interposer and the processing device, and a passive device located on or inside the interposer and electrically connected to the power management integrated circuit device.


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