The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Sep. 11, 2020
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventor:

Masanobu Shirakawa, Chigasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); G11C 16/26 (2006.01); G11C 11/56 (2006.01); H01L 27/1157 (2017.01); G11C 7/06 (2006.01); G11C 16/34 (2006.01); H01L 27/11582 (2017.01); G11C 16/10 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G11C 16/26 (2013.01); G11C 7/06 (2013.01); G11C 11/5628 (2013.01); G11C 11/5642 (2013.01); G11C 11/5671 (2013.01); G11C 16/10 (2013.01); G11C 16/3459 (2013.01); H01L 27/1157 (2013.01); H01L 27/11582 (2013.01); G11C 7/1039 (2013.01); G11C 16/0483 (2013.01); G11C 2211/562 (2013.01); G11C 2211/563 (2013.01); G11C 2211/5621 (2013.01); G11C 2211/5641 (2013.01); G11C 2211/5642 (2013.01);
Abstract

According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first blocks including a memory cell capable of storing data of one bit, a second block including a memory cell capable of storing data of two or more bits. The semiconductor memory stores first data in a first latch circuit, and second data in a second latch circuit, and writes the first data into one of the first blocks in page units, and the second data into one of the first blocks in page units. The semiconductor memory writes data of at least two pages into the second block, using the first data stored in the first latch circuit and the second data stored in the second latch circuit.


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