The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 08, 2022

Filed:

Sep. 29, 2017
Applicant:

Intel Corporation, Santa Clara, CA (US);

Inventors:

Venkateswara Madduri, Austin, TX (US);

Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US);

Mark Charney, Lexington, MA (US);

Robert Valentine, Kiryat Tivon, IL;

Jesus Corbal, King City, OR (US);

Binwei Yang, Austin, TX (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 9/302 (2018.01); G06F 9/30 (2018.01); G06F 7/544 (2006.01); G06F 17/14 (2006.01); G06F 7/48 (2006.01);
U.S. Cl.
CPC ...
G06F 9/3001 (2013.01); G06F 7/4812 (2013.01); G06F 7/5443 (2013.01); G06F 9/30036 (2013.01); G06F 17/142 (2013.01);
Abstract

Apparatus and method to transform complex data including a processor that comprises: multiplier circuitry to multiply packed complex N-bit data elements with packed complex M-bit data elements to generate at least four real products; adder circuitry to subtract a first real product from a second real product to generate a first temporary result, subtract a third real product from a fourth real product to generate a second temporary result, add the first temporary result to a first packed N-bit data element to generate a first pre-scaled result, subtract the first temporary result from the first packed N-bit data element to generate a second pre-scaled result, add the second temporary result to a second packed N-bit data element to generate a third pre-scaled result, and subtract the second temporary result from the second packed N-bit data element to generate a fourth pre-scaled result; and scaling circuitry to scale the pre-scaled results.


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