The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Mar. 27, 2020
Applicant:

Rohm Co., Ltd., Kyoto, JP;

Inventors:

Masaki Nagata, Kyoto, JP;

Takefumi Fujimoto, Kyoto, JP;

Assignee:

ROHM CO., LTD., Kyoto, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
H01L 29/1095 (2013.01); H01L 29/086 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/7813 (2013.01);
Abstract

A semiconductor device includes an n-type semiconductor substrate which includes an n-type impurity having a diffusion coefficient less than a diffusion coefficient of phosphorus, an n-type epitaxial layer which includes a high concentration region, an intermediate concentration region and a low concentration region formed in this order from the semiconductor substrate side and has a concentration gradient in which an n-type impurity concentration is decreased in a downward step-wise manner from the semiconductor substrate toward a crystal growth direction by the high concentration region, the intermediate concentration region and the low concentration region, and a trench structure which includes a trench formed in the low concentration region, an insulating layer formed on an inner wall of the trench and an embedded electrode which is embedded in the trench across the insulating layer.


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