The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Apr. 22, 2020
Applicant:

SK Hynix Inc., Icheon-si, KR;

Inventors:

Hye Hyeon Byeon, Icheon-si, KR;

Il Young Kwon, Icheon-si, KR;

Jin Ho Bin, Icheon-si, KR;

Assignee:

SK hynix Inc., Icheon-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/11582 (2017.01); H01L 27/11556 (2017.01); H01L 21/3115 (2006.01); H01L 21/02 (2006.01); H01L 21/311 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/0217 (2013.01); H01L 21/31111 (2013.01); H01L 21/31155 (2013.01); H01L 27/11556 (2013.01);
Abstract

A method of manufacturing a non-volatile memory device includes forming a gate insulation layer on a semiconductor substrate having a source layer. The method also includes forming a silicon nitride layer having a buffer-treated upper surface on the gate insulation layer, wherein the buffer-treated upper surface of the silicon nitride layer has a hardness higher than a hardness of the silicon nitride layer. The method further includes forming a silicon oxide layer on the buffer-treated upper surface of the silicon nitride layer. The method additionally includes alternately forming additional silicon nitride layers and additional silicon oxide layers on the silicon oxide layer to form a stack structure.


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