The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Oct. 28, 2019
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Abbas Ali, Plano, TX (US);

Guruvayurappan Mathur, Plano, TX (US);

Poornika Fernandes, Murphy, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/07 (2006.01); H01L 27/06 (2006.01); H01L 49/02 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0629 (2013.01); H01L 27/0733 (2013.01); H01L 28/75 (2013.01); H01L 29/0653 (2013.01);
Abstract

An integrated circuit (IC) includes a second metal level located between first and third metal levels, a dielectric layer located over the metal levels, and first, second and third vias within the dielectric layer. The first via traverses the first dielectric layer from a surface of the dielectric layer to the first metal level and has a first diameter. The second via traverses the dielectric layer from the surface to the second metal level and has the first diameter. The third via traverses the dielectric layer from the surface to the third metal level and has a second diameter greater than the first diameter. In some implementations the first, second and third metal levels implement a capacitor.


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