The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Jun. 24, 2020
Applicant:

Synopsys, Inc., Mountain View, CA (US);

Inventors:

Sudeep Mondal, Noida, IN;

Paras Mal Jain, Cupertino, CA (US);

Anshul Tuteja, Rhodes, AU;

Assignee:

Synopsys, Inc., Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 30/33 (2020.01); G06F 30/3308 (2020.01); G06F 30/323 (2020.01); G06F 30/3323 (2020.01); G06F 119/12 (2020.01);
U.S. Cl.
CPC ...
G06F 30/3308 (2020.01); G06F 30/323 (2020.01); G06F 30/3323 (2020.01); G06F 2119/12 (2020.01);
Abstract

A method and a system for identifying glitches in a circuit are provided. The method includes identifying a sub-circuit that drives a net from a plurality of nets in a circuit, generating a glitch detection circuit comprising dual-rail encoding from the net to a signal driver of the sub-circuit, modifying the sub-circuit to include the glitch detection circuit, generating an optimized hardware design language (HDL) output file associated with the glitch detection circuit and the sub-circuit, and performing a simulation or a formal verification of the optimized HDL output file to determine whether a signal associated with the net glitches.


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