The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 01, 2022

Filed:

Apr. 09, 2020
Applicant:

Juniper Networks, Inc., Sunnyvale, CA (US);

Inventors:

John Parker, Goleta, CA (US);

Gregory Alan Fish, Santa Barbara, CA (US);

Martin A. Spannagel, San Francisco, CA (US);

Antonio Labaro, Mountain View, CA (US);

Assignee:

Juniper Networks, Inc., Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G02B 6/12 (2006.01); H01L 21/12 (2006.01); G02B 6/122 (2006.01); H01L 21/762 (2006.01); H01L 21/02 (2006.01); H01L 21/306 (2006.01); G02B 6/132 (2006.01); G02B 6/136 (2006.01);
U.S. Cl.
CPC ...
G02B 6/122 (2013.01); G02B 6/132 (2013.01); G02B 6/136 (2013.01); H01L 21/0217 (2013.01); H01L 21/0228 (2013.01); H01L 21/02164 (2013.01); H01L 21/02178 (2013.01); H01L 21/02181 (2013.01); H01L 21/02186 (2013.01); H01L 21/02189 (2013.01); H01L 21/30617 (2013.01); H01L 21/76251 (2013.01);
Abstract

Methods and systems are presented for heterogeneous integration of photonics and electronics with atomic layer deposition (ALD) bonding. One method includes operations for forming a compound semiconductor and for depositing (e.g., via atomic layer deposition) a continuous film of a protection material (e.g., AlO) on a first surface of the compound semiconductor. Further, the method includes an operation for forming a silicon on insulator (SOI) wafer, with the SOI wafer comprising one or more waveguides. The method further includes bonding the compound semiconductor at the first surface to the SOI wafer to form a bonded structure and processing the bonded structure. The protection material protects the compound semiconductor from acid etchants during further processing of the bonded structure.


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