The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Sep. 26, 2018
Applicant:

Globalfoundries U.s. Inc., Santa Clara, CA (US);

Inventors:

Ajey P. Jacob, Malta, NY (US);

Eswar Ramanathan, Malta, NY (US);

Assignee:

GlobalFoundries U.S. Inc., Santa Clara, CA (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 43/00 (2006.01); H01L 43/02 (2006.01); H01L 43/12 (2006.01); H01L 27/22 (2006.01);
U.S. Cl.
CPC ...
H01L 43/02 (2013.01); H01L 27/222 (2013.01); H01L 43/12 (2013.01);
Abstract

Integrated circuits with embedded memory structures, and methods for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes forming first and second conductive interconnects over a semiconductor substrate. The method includes depositing a conductive material over the first conductive interconnect. Also, the method includes forming a memory structure over the conductive material, wherein the memory structure has an uppermost surface distanced from the first conductive interconnect by a first height. Further, the method includes forming an interlayer dielectric over the memory structure and forming a conductive via coupled to the second conductive interconnect, wherein the conductive via has a second height over the second conductive interconnect less than the first height. The method also includes forming first and second contact plugs through the interlayer dielectric. The first contact plug contacts the memory structure and the second contact plug contacts the conductive via.


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