The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Aug. 25, 2020
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Chanho Kim, Seoul, KR;

Joo-Yong Park, Hwaseong-si, KR;

Daeseok Byeon, Seongnam-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 25/18 (2006.01); H01L 23/00 (2006.01);
U.S. Cl.
CPC ...
H01L 25/18 (2013.01); H01L 24/08 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01);
Abstract

A three-dimensional semiconductor memory device, including a peripheral circuit structure including a first metal pad and a cell array structure disposed on the peripheral circuit structure and including a second metal pad. The peripheral circuit structure may include a first substrate including a first peripheral circuit region and a second peripheral circuit region, first contact plugs, second contact plugs, and a first passive device on and electrically connected to the second contact plugs. The cell array structure may include a second substrate disposed on the peripheral circuit structure, the second substrate including a cell array region and a contact region. The cell array structure may further include gate electrodes and cell contact plugs. The first passive device is vertically between the gate electrodes and the second contact plugs and includes a first contact line. The first metal pad and the second metal pad may be connected by bonding manner.


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