The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 25, 2022

Filed:

Apr. 10, 2020
Applicant:

Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu, TW;

Inventors:

Jeng Chang Her, Tainan, TW;

Cha-Hsin Chao, Taipei, TW;

Yi-Wei Chiu, Kaohsiung, TW;

Li-Te Hsu, Shanhua Township, TW;

Ying Ting Hsia, Kaohsiung, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/52 (2006.01); H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 21/3115 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01);
U.S. Cl.
CPC ...
H01L 21/76829 (2013.01); H01L 21/0234 (2013.01); H01L 21/02321 (2013.01); H01L 21/31155 (2013.01); H01L 21/76834 (2013.01); H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H01L 23/53295 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02126 (2013.01); H01L 21/02167 (2013.01);
Abstract

In a method for manufacturing a semiconductor device, a first interlayer dielectric layer is formed over a substrate. First recesses are formed in the first interlayer dielectric layer. First metal wirings are formed in the first recesses. A first etch-resistance layer is formed in a surface of the first interlayer dielectric layer between the first metal wirings but not on upper surfaces of the first metal wirings. A first insulating layer is formed on the first etch-resistance layer and the upper surfaces of the first metal wirings.


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