The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 25, 2022
Filed:
Jun. 25, 2020
Applicant:
Synopsys, Inc., Mountain View, CA (US);
Inventor:
Adam D. Cron, Hilton Head Island, SC (US);
Assignee:
Synopsys, Inc., Mountain View, CA (US);
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/3177 (2006.01); G01R 31/3181 (2006.01); G01R 31/3185 (2006.01);
U.S. Cl.
CPC ...
G01R 31/3177 (2013.01); G01R 31/31813 (2013.01); G01R 31/318533 (2013.01); G01R 31/318541 (2013.01); G01R 31/318575 (2013.01);
Abstract
An augmented simulation model can be created of an integrated circuit (IC) design by inserting a switch in a simulation model of the IC design between an output of a scan cell and an input of a combinational logic cloud. A simulation enable signal can be used to control the switch. Next, an IC design simulation environment can be generated based on the augmented simulation model. The IC design can be verified by using the IC design simulation environment. The simulation enable signal can be activated when the combinational logic cloud is desired to be simulated by the IC design simulation environment.